- 8 June 2005 -

LETI uses HfSiON for MOS gates

French R&D lab LETI shas successfully fabricated metal gate transistors with a high k gate dielectric on 300mm wafers.The results came as part of its Nanotec 300 research platform for the 45nm and 32nm nodes, which it first unveiled a year ago.

The wafers were produced in cooperation with the Crolles2 Alliance: STMicro-electronics, Freescale Semiconductors and Philips Semiconductors; both LETI and Crolles2 are located in Grenoble, France.

LETI said it has shown that it is possible to integrate high k dielectric insulators, namely hafnium silicon oxynitride (HfSiON), and metal gates into advanced MOS structures on 300mm wafers, thus drastically reducing parasitic leakage current and avoiding gate depletion. Circuits produced with this technology combine very low off-state power consumption with high performance and speed, according to the R&D lab.

The new gate stack withstands thermal treatments of 1000 degrees Celcius-10sec, and is hence fully compatible with standard planar CMOS architectures, LETI said.

"This demonstration ranks among the best performances shown worldwide to date," OIivier Demolliens, department head of Nanotec 300, said in a statement. "It shows that we are fully operational on our 300mm platform in integrating the most advanced front end materials.

"Between now and the end of 2005, we will combine the added benefits of high performance interconnects based on low k materials (with a dielectric constant, or k value, of 2.2) that significantly reduce parasitic capacitance."