- 21 June 2005 -

Cooling for denser packaging
and reliability


Developed at the Georgia Institute of Technology, a wafer-level fabrication technique including polymer pipes will allow electronic and cooling interconnections to be made simultaneously, using automated manufacturing processes.

The low-temperature technique, compatible with conventional microelectronics manufacturing processing, allows fabrication of the microfluidic cooling channels without damage to ICs.

The on-chip microfluidic technique was described at the annual IEEE International Interconnect Conference in San Francisco, CA and sponsored by the Microelectronics Advanced Research Corporation and DARPA.

“This scheme offers a simple and compact solution to transfer cooling liquid directly into a gigascale integrated (GSI) chip, and is fully compatible with flip-chip packaging,” said Bing Dang, graduate research assistant in Georgia Tech’s School of Electrical and Computer Engineering.

“By integrating the cooling microchannels directly into the chip, we can eliminate a lot of the thermal interface issues that are of great concern.”

The Georgia Tech approach allows a simple monolithic fabrication of cooling channels directly onto ICs using a CMOS-compatible technique at temperatures of less than 260 degrees Celsius.

“Once the IC is fabricated, it cannot withstand high temperatures without causing damage. People are looking at liquid cooling in all forms to solve the thermal issues affecting advanced integrated circuits, and the goal is to prevent damage to the chips," said Dang.

The Georgia Tech researchers, who include Paul Joseph, Muhannad Bakir, Todd Spencer, Paul Kohl and James Meindl, begin by etching trenches more than 100 microns deep on the back of the silicon wafer. They then spin-coat a layer of high-viscosity sacrificial polymer onto the back of the chip, filling in the trenches. A simple polishing step removes excess polymer.

The filled trenches are then covered by a porous overcoat, and the chip gradually heated in a nitrogen environment. The heating causes the sacrificial polymer filling the trenches to decompose, leaving the channels through the porous overcoat, with the microfluidic channels behind. The porous overcoat is then covered with another polymer layer to make a watertight system.

In addition to the cooling channels, the researchers have also built through-chip holes and polymer pipes that would allow the on-chip cooling system to be connected to embedded fluidic channels built into a printed wiring board.

They have already demonstrated that the on-chip microfluidic channels can be connected at the same time the IC is connected electronically – using flip-chip bonding.

The system would use buffered de-ionized water as its coolant. Self-contained cooling systems would circulate coolant using a centimeter-size micro-pump, while more complex equipment could use a centralised circulation system. The researchers have r demonstrated that their microchannels can withstand pressure of more than 35psi.

Calculations show that the system, which can have a straight-line or serpentine microchannel configurations, should be able to cool 100W/sq.cm. Heat removal capacity depends on the flow rate of the coolant and its pressure, with smaller diameter microchannels more efficient at heat transfer.

The technology is expected to be used first in high-performance specialty processors that can justify the cost of the cooling system. So far, the researchers have demonstrated continuous liquid flow on a chip for several hours without failure, but additional testing is still needed to confirm long-term reliability.

Eliminating large heat sinks, heat spreaders, and high-aspect ratio fins, the technology allows denser packaging of ICs, making 3D packaging feasible.

“The challenge of 3D integration now is that if you have several chips stacked on one another, there is no way to cool the chips in between,” Dang said. “If we have microchannels on the back side of each chip, we could pump liquid through them and cool all of the chips.”