- 24 May 2005 -

Faster Floating point FFT IP core for FPGA

4DSP Inc of Reno, Nevada, have released a new Floating Point Fast Fourier Transform core that is IEEE-754 compliant. The IP core was designed for use in the newer generation of high performance programmable devices, now available from FPGA vendors like Xilinx and Altera.

The FFT core performs and transforms on complex data ranging from 256 points to 1M points with external memory, if necessary, such as QDR SRAM, closely coupled to the internal logic of the FPGA.

Based on a radix-32 architecture, it allows users to change the transform length "on the fly", without having to reconfigure the programmable device. The flexibility engineered into its design makes this FFT core the component for systems that may change mission rapidly in their application design or for systems whose algorithms are complex in nature or may require flexibility in mission assignment.

"We did not expect to reach this level of performance in an FPGA. This has typically been done in an ASIC, which is increasingly more expensive to develop and requires a specific board architecture.

"To produce a flexible and lower cost device, that is capable of performing a 1024 points Floating Point FFT in 11.4 microseconds using a single core, is far beyond our original expectations," says Pierrick Vulliez, 4DSP's CTO.

"For example, when applied to Video 2D transforms with 1024 x 1024 images, a single core can process 42 frames/sec."

New advancements in FPGA gate densities, combined with efficient, tightly written VHDL cores, allow multiple cores to co-exist inside a single FPGA device. In new chips like the Altera Stratix-II and Xilinx Virtex-4 FPGAs, four cores can be implemented in parallel, offering a double-digit acceleration factor compared to currently available floating-point DSP devices.

Contact: info@4dsp.com