- 1st August 2005 -

Focus on FET and screen grid FET

Innos has announced that a joint project led by Imperial College, London, has demonstrated the potential for high-speed low power applications using strained-Si transistors. The project, funded by the EPSRC, studies the re-designing and fabricating of transistors for applications in medicine.

High performance, low power electronics is becoming ubiquitous in a vast range of everyday products, from laptops to cameras. A crucial and common requirement is these applications need to be fast and run for long periods of time on small lightweight batteries.

The project conducted by Imperial College London and facilitated by Innos in its cleanroom aimed to demonstrate the viability of the new transistors for applications in health monitoring, for example, diagnostic imaging, with a particular emphasis on home health monitoring.

The project tested the feasibility of the fabricated and newly designed strained-Si surface channel and buried channel Field-Effect-Transistor. It also demonstrated and characterised simple monolithically integrated circuits using strained-Si FETs and reduced temperatures.

“Large foundries have a tendency to be very inflexible with respect to changes to standard fabrication processes,” explains senior lecturer at Imperial College London, Dr Kristel Fobelets.

“We decided to involve Innos because its facilities contain all the know-how and standard fabrication tools available, and was very flexible in terms of requirements. It also has strong links with the EPSRC. The personal relationship we built with Innos is strong and based on two-way communication and feedback.”

Sales and marketing manager at Innos, Dr Alec Reader, commented: “ We have enjoyed a good relationship and are planning to work with Imperial College London again, studying the screen-grid FET, a novel transistor structure invented by Dr Kristel Fobelets that again deviates from a traditional FET structure, something we are well positioned to investigate.”