- 27 September 2006 -

IMEC (sub-)32nm research platform shows momentum in record IEDM papers

IMEC, the independent nanoelectronics and nanotechnology research institute, will present together with its core partners 17 papers at the IEEE International Electron Devices Meeting (December 11 -13, 2006, San Francisco). This record in number of papers at one of the world’s leading conferences on semiconductor technologies, showcases the success of IMEC’s global R&D efforts to create solutions for (sub-)32nm scaling.

Several advances will be reported in the scaling of logic technology options. For extending bulk CMOS into the 45/32nm nodes, IMEC has developed an alternate integration process for their FUSI technology that is more manufacturing friendly without the need for a CMP (chemical mechanical polishing) step. It is based on using a planarizing resist and etch-back to open the FUSI gates.

On the alternate metal gate option, i.e. metal-gate first approach or deposited metals, IMEC reports on MoOx as a promising pFET.

Two papers on FinFET CMOS will be reported demonstrating the impact of fin line-edge roughness on device characteristics, as well as the process technology to double or quadruple the fin density per area.

Beyond silicon as substrate, IMEC will demonstrate a short channel Ge pMOS device built with Si-compatible process techniques.

Reliability is an important factor in any semiconductor process development and therefore forms an integral part of the technology development programs at IMEC. IMEC will present several results on reliability both in the field of 32nm CMOS and Flash memories. A detailed electrical and failure analysis of the impact of using Cu contacts on the CMOS front-end yield and reliability will be reported. For the first time, NBTI (negative biased temperature instability) degradation experiments under AC conditions at frequencies up to 2GHz in SiON-based dielectrics will be presented. It will also be shown that ultra-fast progressive breakdown in HfO2/TaN/TiN gate stacks n/p-MOSFETs only occurs during substrate injection. A model to explain this polarity dependence will be presented.
Papers on non-volatile memory will focus on reliability modeling. A model that allows describing the leakage current through high-k insulators will be shown. This model is essential to predict the long-term retention time for new-generation Flash technologies incorporating high-k interpoly dielectrics and/or tunnel layers. Also a consistent model for the description of the retention of localized charge trapping devices based on channel hot carrier injection into nitride layers will be presented.

“The results that will be presented at IEDM 2006 show that IMEC and its core partners have made significant advances in fundamental understanding the bottlenecks in (sub-)32nm scaling and developing the generic process steps, modules and devices,” said Luc Van den hove, Vice President Silicon Process and Device Technology at IMEC. “We are excited that the combined effort of the IMEC research team and our core partners result in solutions for continued CMOS scaling feeding directly into development teams.”
Besides results achieved in the (sub-)32nm research platform, IMEC will also report a new integration process for backside thinned CMOS imagers with increased performance.

Further information on IMEC can be found at www.imec.be