06th December 2006

PATENT NEWS: MOCVD Susceptor for Nitrides from Nakamura & DenBaars of Cree

In recent US Patent #7,122,844, Shuji Nakamura, Steven DenBaars, Max Batres and Michael Coulter; (Santa Barbara, CA) of Cree, Inc. (Goleta, CA) describe an improved susceptor for MOCVD growth of nitride and other epilayers.

A susceptor for holding semiconductor wafers in an MOCVD reactor during growth of epilayers on the wafers is disclosed. It comprises a base structure made of a material having low thermal conductivity at high temperature, and has one or more plate holes to house heat transfer plugs. The plugs are made of a material with high thermal conductivity at high temperatures to transfer heat to the semiconductor wafers.

The patent claims to address the disadvantages of existing susceptors which include ‘memory’ effects from residual impurities deposited in previous runs.Another disadvantage of conventional susceptors is that the heating element heats the entire susceptor, not just the areas under or around the wafers and they are difficult to manufacture.

Reduced amounts of reactants are deposited on the susceptor embodiments disclosed herein, thereby reducing unwanted impurities during subsequent fabrication steps. The epitaxial layers can also be grown using less energy and consuming less source material, because most of the heat from the reactor's heating element passes through the heat transfer plugs instead of heating the entire susceptor. The susceptor can also be manufactured using less complex processes because it does not need to be machined from a solid piece of graphite. Also, the heat transfer plugs can be more easily machined so that their surface adjacent to the wafer has a convex or concave shape to compensate for any temperature non-uniformity.

Cree has as usual produced several other patents in related fields. For instance US Patent #7,138,291 DA McClure, et al., describe ‘Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices’.
It involves a method for treating a silicon carbide substrate for improved epitaxy and for use as a precursor in the manufacture of devices such as LEDs. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer to form a dopant profile. This then goes through a number of follow on processes such as annealing and growing an epilayer on the implanted first surface of the wafer.

Cree has been working to fix certain problems in this area. An important parameter for LEDs is the forward voltage drop between the anode and the cathode during forward bias operation. In particular, it is desirable for it to be as low as possible to reduce power consumption and increase the overall efficiency of the device. Despite the advance of the '606 patent, there remains a measurable voltage drop at the interface between a conventional silicon carbide substrate and the conductive buffer layer.
In another US Patent #7,135,747 for AW Allen, et al.. ‘Semiconductor devices having thermal spacers’ are reported. Then in US Patent #7,135,715 Saxler et al., describe ‘Co-doping for Fermi level control in semi-insulating Group III nitrides’.

III-nitride layers include doping a III-nitride layer with a shallow level p-type dopant and doping the nitride layer with a deep level dopant, e.g. a deep level transition metal dopant. Such layers and/or method may also include doping a Group III nitride layer with a shallow level dopant having a concentration of less than about 1x1017 cm-3 and doping the III-nitride layer with a deep level transition metal dopant. The concentration of the deep level transition metal dopant is greater than a concentration of the shallow level p-type dopant.

Finally, US Patent #7,135,359 for Anant Agarwal, et al., reports ‘Manufacturing methods for large area silicon carbide devices’.

Large area silicon carbide devices, such as light-activated thyristors, having only two terminals are provided. The devices are selectively connected in parallel by a connecting plate and have a portion of the gate region exposed so as to allow light of about 3.25 eV to activate the gate. They may be symmetric or asymmetrical.

Several such thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate, Cree says

Web: www.cree.com.